Hardware implementation of intelligent systems

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Robust estimation of bacterial cell count from optical density

Optical density (OD) is widely used to estimate the density of cells in liquid culture, but cannot be compared between instruments without a standardized calibration protocol and is challenging to relate to actual cell count. We address this with an interlaboratory study comparing three simple, low-cost, and highly accessible OD calibration protocols across 244 laboratories, applied to eight strains of constitutive GFP-expressing E. coli. Based on our results, we recommend calibrating OD to estimated cell count using serial dilution of silica microspheres, which produces highly precise calibration (95.5% of residuals <1.2-fold), is easily assessed for quality control, also assesses instrument effective linear range, and can be combined with fluorescence calibration to obtain units of Molecules of Equivalent Fluorescein (MEFL) per cell, allowing direct comparison and data fusion with flow cytometry measurements: in our study, fluorescence per cell measurements showed only a 1.07-fold mean difference between plate reader and flow cytometry data

Task-level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures

This paper presents spade, a system for partitioning designs onto multi-fpga architectures. The input to spade is a task graph, that is composed of computational tasks, memory tasks and the communication and synchronization between tasks. spade consists of an iterative partitioning engine, an architectural constraint evaluator, and a throughput optimization and rtl design space exploration heuristic. We show how various architectural constraints can be effectively handled using an iterative partitioning engine. 1 Introduction The primary focus of existing multi-fpga partitioning research is rtl or gate level partitioning. A popular and advantageous system-synthesis approach is to perform behavioral partitioning prior to, or during, the high-level synthesis process [1]. Although several interesting features may be found in existing multi-fpga partitioning techniques, it is very difficult to adapt any of them to suite partitioning for a generic multi-fpga board. This is because, stateo..

A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures

This paper presents a novel technique to perform dynamic high-level exploration of a behavioral specification that is being partitioned for a multi-device architecture. The technique, unlike in traditional HLS, performs a global search on the four-dimensional design space formed by multiple partition segments of the behavior. Hence, the proposed technique effectively satisfies the global latency constraint on the entire design, as well as the area constraints on the individual partition segments. Since the technique is based on a rigorous exploration model, it employs an efficient lowcomplexity heuristic instead of an exhaustive search. We have provided a number of results by integrating the exploration technique with two popular partitioning algorithms: (i) simulated annealing and (ii) fiducciamattheyses. The proposed technique is highly effective in guiding any partitioning algorithm to a constraint satisfying solution, and in a fairly short execution time. At tight constraint values..